1. Field of the Invention
The present invention relates in general to an electro-optical device and method of forming the same and method of driving the same. More particularly, it relates to such an active matrix type device and a method of manufacturing the same with an appropriate arrangement of driver transistors.
2. Description of the Prior Art
In recent years, the active matrix technique for driving liquid crystal displays has been broadly studied and put in practice. A conventional active matrix circuit comprises thin film transistors (TFT) which control accumulation of electric charge in capacitances formed between respective pixel electrodes and a common opposite electrode with a liquid crystal layer sandwiched therebetween.
Usually, TFTs of only one conductivity type are utilized for constructing the active matrix circuit. Another type active matrix circuit, however, has recently been proposed as described in Japanese Patent Application No. Hei 3-76785 utilizing the so-called modified transfer gate. Such an unaccustomed circuit is employed because the liquid crystal display can operate with a symmetrical driving polarity with the circuit, e.g., as demonstrated in Japanese Patent Application No. Hei 3-208648. Namely, it is difficult for active matrix circuits to realize a symmetrical operation by the use of only one conductivity type.
It is needed for stabilizing image appearing on a display to maintain constant the driving voltage applied across the liquid crystal layer, i.e. the voltages of the respective pixel electrodes with reference to the common opposite electrode with a liquid crystal of the liquid crystal display therebetween. This, however, is difficult for several reasons. The most substantial reason is leakage of electric charge accumulated in the capacitances formed across the liquid crystal layer due to OFF current of the TFTs. There also exists leakage through the capacitance itself. The leakage current through the capacitance, however, is smaller than the leakage current through the TFT turned off by about one order of magnitude. If the leakage current is significant, the image displayed is periodically disturbed in synchronism with vertical scan, i.e. at the frame frequency. Another reason for fluctuation of the voltages (.DELTA.V) across the liquid crystal is coupling of the pixel electrode with the gate signal because of the parasitic capacitance formed between the gate electrode and the pixel electrode.
The fluctuation of the voltages .DELTA.V across the liquid crystal due to the parasitic capacitance formed between the gate electrode and the pixel electrode is expressed by the equation EQU .DELTA.V=C'V.sub.G /(C.sub.LC +C') (1)
where C' is the parasitic capacitance formed between the gate electrode and the pixel electrode, V.sub.G is the gate pulse applied to the gate electrode and C.sub.LC is the capacitance across the liquid crystal layer at the pixel. The fluctuation of the voltages .DELTA.V is theoretically independent from the magnitude or the polarity of signals applied to the data lines, i.e. applied to the sources of the TFTs.
The capacitance C.sub.LC may be increased as compared to the capacitance C' in order to solve the problem associated with the fluctuation of the voltages .DELTA.V. This is accomplished by forming source and drain regions in accordance with the self-aligning technique in order to decrease the capacitance C' or by inserting an auxiliary capacitance in parallel to the liquid crystal layer in order to increase the apparent value of the denominator of the above equation. The later solution is illustrated in FIGS. 1(A) and 2(A). The time constant of discharging electric charge from the pixel is increased by provision of such an auxiliary capacitance. The above equation is modified in this case as EQU .DELTA.V=C'V.sub.G /(C.sub.LC +C'+C) (2)
where C is the auxiliary capacitance. The fluctuation voltage .DELTA.V is reduced by selecting C to be relatively large.
The auxiliary capacitances C are formed between the respective pixel electrode and ground lines X.sub.n ' extending in parallel to and provided respective for corresponding row lines X.sub.n which supply addressing gate signals to pixels arranged on the rows. This configuration is typically illustrated in FIGS. 1(B) and 2(B). For example, the auxiliary capacitance C is formed by arranging the ground lines X.sub.n ' to pass just under the pixel electrode C.sub.LC as illustrated with a hatched area in FIG. 3. This structure is described in Japanese Patent Application No. Hei 3-163873. In this case, however, since particular electrode lines (the ground lines X.sub.n ') have to be formed in addition, the aperture ratio is then decreased to reduce the brightness of the display.
This shortcoming may be removed by utilizing the row lines X.sub.n also as the ground lines X.sub.n ' as illustrated in FIGS. 1(C) and 2(C) in which each pixel electrode overlies the row line X.sub.n+1 of the next pixel. In this case, since no additional electrode lines are formed, the aperture ratio is not decreased. It is, however, difficult to arrange the pixel electrodes and the row lines in an effective layout and to prevent interference between a respective pixel electrode and the TFT associated with the pixel located just below the electrode. Namely, no effective circuit design and layout has been proposed which can provide a sufficient auxiliary capacitance and a high yield with a high visual performance.
Recently, the use of CMOS transfer gates has been proposed to solve the above problem as discussed, for example, in Japanese Patent Application No. Hei 2-178632. In this case, when a negative pulse and a positive pulse of the same voltage level V.sub.G are applied respectively to the gate electrodes of PMOS and NMOS transistors at the same time, the fluctuation of the voltages (.DELTA.V) across the liquid crystal due to the parasitic capacitances C.sub.1 and C.sub.2 formed between the gate electrodes and the pixel electrode is expressed by the equation EQU .DELTA.V=(C.sub.1 -C.sub.2)V.sub.G /(C.sub.1 +C.sub.2 +C.sub.LC) (3)
where C.sub.LC is the capacitance across the liquid crystal layer at the pixel. The fluctuation can be removed by making equal the capacitances C.sub.1 and C.sub.2. The provision of the two transistors for each pixel also makes possible to operate even if one of the transistors is fault. The fluctuation, however, becomes large in this case if the parasitic capacitance is large. Although the PMOS transistor and the NMOS transistor of adjacent pixels share the same row line, it may be possible to separate lines respectively for supplying gate signals to these transistors as described in Japanese Patent Application No. Hei 2-178632. Of course, the provision of the separate lines reduces the aperture ratio and therefore the brightness.
In general, electric charge leakage takes place through TFTs from the pixel electrodes in active matrix circuits. The leakage has been compensated in prior arts by providing auxiliary capacitances. The transfer gates as illustrated in FIGS. 4(A) and 5(A) are provided with the auxiliary capacitance C.sub.1 and C.sub.2 in the same manner. In this case, making use of the feature of the transfer gate, the gate (row) lines X.sub.n and X.sub.n ' are formed overlapping with the pixel electrode in order to adjust the fluctuation voltage .DELTA.V at zero by forming the capacitances C.sub.1 and C.sub.2 to equal each other as illustrated in FIG. 4(B) and FIG. 5(B). It is noted that the gate lines are grounded unless no signal is applied thereto. As a result, it has been expected by employing this fashion to obtain high quality images with a large aperture ratio but without a need for providing particular lines to form the auxiliary capacitances C.sub.1 and C.sub.2.
It is, however, difficult to make the capacitances C.sub.1 and C.sub.2 exactly equal when the capacitances C.sub.1 and C.sub.2 become large. If source and drain regions of a TFT is formed by self-aligning technique, the parasitic capacitance inherently formed between the drain and the gate is usually within 10% of the capacitance associated with the pixel electrode. If two TFTs are formed for one pixel, the difference between the capacitances of the two TFTs can be within 30%. In this case, the fluctuation voltage .DELTA.V can be limited within about 3% of the gate voltage V since (C.sub.1 -C.sub.2) can be limited within about 3% of the capacitance C.sub.LC associated with the pixel electrode in Equation (3).
On the other hand, when the capacitance formed between the drain and the gate is enhanced as illustrated in FIG. 4(B) and FIG. 5(B), the enhanced capacitance C.sub.1 or C.sub.2 is as large as the capacitance C.sub.LC associated with the pixel electrode in order to make effective the auxiliary function. Accordingly, even if the difference between the enhanced capacitance C.sub.1 and C.sub.2 is limited within 10%, (C.sub.1 -C.sub.2) becomes about 10 to 20% of the capacitance C.sub.LC associated with the pixel electrode in Equation (3). In practice, the fluctuation voltage .DELTA.V becomes more large since the difference between the enhanced capacitance C.sub.1 and C.sub.2 usually fluctuates more widely due to variation of the gate width and the overlapping area and since the enhanced capacitance C.sub.1 or C.sub.2 is usually designed to be 10 or more times as large as the capacitance C.sub.LC associated with the pixel electrode.